17th Asia and South Pacific Design Automation Conference ASP-DAC 2012

Asia and South Pacific Design Automation Conference (ASP-DAC ) is dedicated to VLSI design automation in Asia and South Pacific region including topics such as:

• System-Level Synthesis and Optimization: hardware-software partitioning, System-on-chip and multi-processor SoC (MPSoC) design methodology, IP/platform-based design, hardware-software co-design, low power system design and application-specific instruction-set processor (ASIP) synthesis
• System-Level Modeling and Simulation/Verification: specification, System-level modeling, performance analysis, language, hardware-software co-simulation/co-verification and system-level simulation/verification
• Embedded and Real-Time Systems: real-time system design, Embedded system design, middleware, OS, memory/cache optimization, compilation techniques, interfacing and software issues
• System-Level Memory/Communication Design and Networks on Chip: network-on-chip (NoC) design methodologies and CAD, Communication-based architecture design, system communication architecture, interface synthesis, low power communication design and memory architecture
• Validation and Verification for Behavioral/Logic Design: symbolic simulation, Logic simulation, equivalence checking, formal verification, assertion-based verification, transaction-level/RTL and gate-level modeling and validation, constrained-random testbench generation and coverage-analysis
• High-Level/Behavioral/Logic Synthesis and Optimization: technology-independent optimization, High-Level/behavioral/RTL synthesis, interaction between logic design and layout, technology mapping, resource scheduling, sequential and asynchronous logic synthesis, synthesis and allocation
• Timing, Power, Thermal Analysis and Optimization: statistical performance analysis and optimization, Deterministic and statistical static timing analysis, power and leakage analysis, low power design, thermal analysis, power/ground and package analysis and optimization
• Physical Design: partitioning, Floor planning, buffer insertion, placement, interconnect planning, routing, post-placement optimization, clock network synthesis, package/PCB routing and layout verification
• Signal/Power Integrity, Interconnect/Device/Circuit Modeling and Simulation: clock and bus analysis, Signal/power integrity, package modeling, interconnect and substrate modeling/extraction, circuit simulation, device modeling/simulation, high-frequency and electromagnetic simulation of circuits