3rd International Workshop on Design Automation (IWoDA 2021)

The 3rd International Workshop on Design Automation (IWoDA 2021) covers topics such as:

• Advanced multimedia application
• 2D/3D on-chip power delivery network analysis and optimization
• Analog Design, Simulation, Verification and Test
• Analog and mixed-signal/RF test
• Analog/mixed-signal modeling and simulation techniques
• Analog layout, verification and simulation techniques
• Architectural low-power design technique
• Analog/mixed-signal/RF synthesis
• Architectures for machine learning and artificial intelligence
• Architecture, tool and methodology for secure hardware
• ATPG, BIST and DFT
• Artificial intelligence hardware and systems
• Autonomous Systems Architectures
• Automotive system design and optimization
• Autonomous Systems Safety and Reliability
• Autonomous Systems Design Tools and Methodologies
• Biochip and biodata processing etc
• Big data application
• CAD for memory circuits
• Biomedical application
• Circuit-level formal verification
• CAD for nanotechnology, MEMS, 3D IC, quantum computing etc
• Combinational, sequential and asynchronous logic synthesis
• Clock network synthesis
• Communication-centric system design, application, and simulation
• Communication traffic and modeling
• Cross-Layer Power Analysis and Low-Power Design
• Compiler and toolchain
• Cyber physical system
• Cross-layer security
• Cyber-physical systems and IoT security
• Cyber-physical systems and Internet-of-Things (IoT) platforms
• Design for manufacturability, yield, and defect tolerance
• Dependable architecture
• Design for security and security primitive
• Design for reliability, aging, and robustness
• Design of Cyber-physical Systems and IoT
• Design methodology for mobile, wearable and Internet of Things devices
• Deterministic/statistical timing and performance analysis and optimization
• Design Verification and Validation
• Device/circuit-level simulation tool and methodology
• Device/circuit/interconnect modeling and analysis
• Digital Design, Timing and Simulation
• Digital and Analog Circuits
• Domain-specific embedded libraries (e.g., for machine learning)
• Domain-specific architecture
• Embedded and Cross-Layer Security
• Electromobility
• Embedded Software
• Embedded Memory, Storage and Networking
• Emerging Device Technologies
• Embedded System (beyond chip) Design Methodologies
• Emerging models of computation
• Emerging interconnect technology and application
• Energy-storage/smart-grid/smart-building design and optimization
• Energy harvesting and battery management
• Fault analysis, detect and tolerance
• Extraction, TSV and package modeling
• Floorplanning, partitioning and placement
• Fault modeling and simulation
• Hardware Security
• Hardware for large-scale data analytics and processing
• High-level synthesis tool and methodology
• High-frequency electromagnetic simulation of circuit
• HW/SW co-design, co-simulation and co-verification
• Human-computer interface
• Inter/intra-chip interconnect and network, and interface and I/O
• In-Package and On-Chip Communication and Networks-on-Chip
• Internet of things
• Interconnect planning and synthesis
• Kernel, middleware and virtual machine
• IP/platform-based SoC design
• Low-power design and methodology
• Logic synthesis and physical design technique for FPGA
• Machine learning architecture
• Machine Learning and Artificial Intelligence Architectures
• Manufacturing Test and Reliability
• Machine learning techniques for verification
• Memory test and repair
• Many- and multi-core SoC architecture
• Model- and component-based embedded system/software design
• Mixed-signal design consideration
• Networks-on-chip and NoC-based system design
• Near-Memory and In-Memory Computing
• New transistor/device and process technology: spintronic, phase-change, single-electron etc
• Neuromorphic and brain-inspired computing
• Online test and fault tolerance
• Noise analysis
• Package/PCB/3D-IC routing
• Optical/photonic interconnect and network
• Placement and routing optimization
• Physical Design and Verification, Lithography and DFM
• Power modeling, analysis and simulation
• Post layout and post-silicon optimization
• Power-aware analog circuit/system design
• Power/ground and package modeling, analysis and optimization
• Real-time system
• Rack-scale interconnect and network
• Reliability, aging and soft error analysis
• Reconfigurable and self-adaptive SoC architecture
• Resource allocation for heterogeneous computing platform
• Resilience under manufacturing variation
• RTL and gate-leveling modeling, simulation and verification
• Reticle enhancement, lithography-related design and optimization
• Security modeling and analysis
• RTL/Logic Level and High-level Synthesis
• Signal/power integrity, EM modeling and analysis
• Security vulnerabilities in artificial intelligence
• Storage software and application
• SoC, Heterogeneous, and Reconfigurable Architectures
• System test and 3D IC test
• Storage system and memory architecture
• System-level design exploration, synthesis and optimization
• System verification and analysis
• System-level modeling, simulation and validation tools/methodology
• System-level formal verification
• Technology mapping
• System-on-Chip Design Methodology
• Time-Critical System Design
• Thermal aware design
• Validation of cognitive systems